The present invention is related to systems and methods for detecting and decoding digital information. More particularly, the present invention relates to systems and methods for detecting and correcting errors associated with an information transfer.
Digital communication systems (e.g., sets of wireless communication devices) and digital storage systems-(e.g., hard disk drives) provide for transfer of different types of information. For example, in the case of communication systems, digital information is transferred substantially in real time from one communication device to another. In contrast, digital information transfer involving digital storage systems typically involves a non-real time transfer of digital information that was previously stored to a storage device. While there are fundamental differences between the aforementioned information transfer approaches, the general goal of both approaches is to transfer information as accurately as possible in the presence of impairments such as noise and inter-symbol interference (ISI).
The goal of increasing the accuracy of information transfer has fueled development of progressively more complex information transfer approaches that include increasingly elaborate error correcting schemes (ECSs). As an example, a state of the art information transfer approach may include a substantial number of parity bits built into the information being transferred. These parity bits introduce redundancy into the signal prior to transmission, and are subsequently used to decode the encoded information. FIG. 1 depicts an exemplary state of the art transfer system tailored for a digital storage system. It should be noted that a typical state of the art system tailored for a digital communication system would typically include the same level of complexity or possibly greater.
Turning to FIG. 1, a block diagram is provided for a known digital storage system 1 that utilizes an elaborate row and column parity approach for error detection and correction. Digital storage system 1 includes an encoder 2 that encodes information bits by interleaving parity bits throughout the original information. Encoder 2 is typically a two-dimensional product code (TPC) encoder. After the original information is encoded, it is provided to recording channel 3 that typically includes various physical and electrical components, such as a read/write head, a read/write head armature, a recording media, a pre-amplifier, or other related circuitry or components.
The encoded information is passed from recording channel 3 to a soft output Viterbi algorithm (SOVA) channel detector 4. SOVA channel detector 4 processes the received encoded information using a bit detection algorithm. The output of SOVA channel 4 includes a combination of hard decisions and reliability estimates (i.e., respective estimates as to the reliability of the respective hard decisions). Both the soft and hard outputs of SOVA channel detector 4 are provided to a decoder 5 that is responsible for de-interleaving the parity bits and decoding the recovered information bits using the parity bits.
Operation of digital storage system 1 is exemplified where original information (e.g., uk=010110) is to be stored in recording channel 3. This original information is represented by Table 1 below.
TABLE 1Original Information (uk)011100The original information, uk, is provided to encoder 2 that encodes the information. Where it is assumed that encoder 2 is a two-dimensional product (TPC) encoder, a parity bit is added to each row and to each column of table 1 to produce an even parity code (i.e., each column and each row contains an even number of 1's). Thus, the original information represented by a 3×2 table is formed into encoded information, ck, that is formed in a 4×3 table. The parity laden 4×3 table is represented as table 2 below.
TABLE 2Original Information Interleaved with Parity (ck)011110000101
For simplicity, the example assumes that each column of table 2 corresponds to a single parity codeword. However, in a typical implementation, this would not be the case as the parity bits would be pseudo-randomly interleaved throughout the original information bits, rather than being placed at the end of each column and row. Thus, a typical implementation would be much more complex.
In this example, the resulting codeword, ck=010111001001, is recorded by recording channel 3. When retrieved from recording channel 3, a signal xk provided from recording channel 3 may be corrupted by noise, nk, resulting in a corrupted signal yk. The noise, nk, may be, for example, additive Gaussian noise. SOVA channel detector 4 receives the corrupted signal, yk, and produces hard decisions and corresponding soft reliability estimates. Decoder 5 receives the output of SOVA channel detector 4 and decodes the output to recover the original information using the interleaved parity information.
In some embodiments, the parity bits may be used in an iterative decoder and detection approach to increase accuracy of the recovered information. An exemplary system 60 using such an iterative decoder and detection approach to increase the accuracy of the recovered information is shown in FIG. 2. A first SOVA channel detector 61 processes information from the read channel, and provides a combination of hard and soft outputs representing the original information and interleaved parity bits. This combination of hard and soft outputs are provided to a first stage decoder 62. First stage decoder 62 includes a row detector 63 and a column detector 64, and a row decoder 66 and a column decoder 67. In addition, first stage decoder 62 includes a delay element 65, and a collection of summers 68, 69 and 71.
The encoded bits are stored in the read channel (not shown) in a table comprising rows and columns such as Table 2 above. Row decoder 63 receives the hard and soft detector outputs from SOVA channel detector 61, and uses the hard and soft detector outputs to decode the rows. Similarly, column decoder 64 receives the hard and soft detector outputs from SOVA channel detector 61, and uses the hard and soft detector outputs to decode the columns. Row decoder 63 and column decoder 64 generate outputs that are combined by summers 68 and 69 with the outputs of SOVA channel detector 61 delayed by delay element 65. The combination of the outputs of SOVA channel detector 61 and column decoder 64 are provided to another row decoder 66. Likewise, the combination of the outputs of SOVA channel detector 61 and row decoder 63 are provided to another column decoder 67. The data provided to row decoder 66 and column decoder 67 is used to decode the respective rows and columns. In particular, row decoder 66 uses information generated by column decoder 64 to further decode the rows, and column decoder 67 uses information generated by row decoder 63 to further decode the rows. This type of iteration in the decoder requires both column and row decoders because each uses information from the other to make decoding decisions.
In addition, there is an iteration between the detector and decoder processes. As shown in FIG. 2, the outputs of the row decoder 66 and column decoder 67 are combined by summer 71 and provided to another SOVA channel detector 72 and to a delay element 73. SOVA channel detector 72 also receives the same input that was provided to SOVA channel detector 61 after passing through delay element 75. SOVA channel detector 72 generates soft and hard outputs that are combined by a summer 74 with the combined outputs of the row decoder 66 and column decoder 67 as delayed by delay element 73. This information is then provided to another channel decoder 76.
Channel decoder 76 provides the same processing implemented by channel decoder 62, thus providing the iterative approach to decoding. Channel decoder 76 includes components 83-91 that correspond to similar components 63-71, respectively. In addition, channel decoder 76 includes a delay element 92 that provides a time delay that is equal to the time delay provided by a delay element 85. The outputs of row decoder 86 and column decoder 87 of channel decoder 76 are combined by a summer 91 with the delayed input to channel decoder 76. The result is the recovered original information bits after a double pass iteration that typically provides for greater error protection.
As will be appreciated from the preceding discussion, while system 60 intuitively provides a reduction in errors, system 60 requires a substantial amount of circuitry. In particular, implementing system 60 involves duplicating detection and decoding logic, and memory. Consequently, system 60 consumes a relatively large amount of area on a semiconductor die, and is also relatively inefficient in terms of power consumption. In addition, all of the iterative processing takes a relatively large amount of time to be performed, which decreases the overall speed of the system. Further, the approach of system 60 may not provide sufficient error reduction even where the increased costs of space and power are sustainable.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for error reduction.